1. Field of the Invention
The present invention relates to a semiconductor memory device including a plurality of memory cells and a method for controlling data write to the semiconductor memory device.
2. Description of the Related Art
In a semiconductor memory device including a plurality of memory cells each of which stores at least 1-bit data, such as an MLC (multi level cell) flash memory device or the like, the threshold voltages of the memory cells which indicate the data therein are different. Therefore, data conversion needs to be performed in one way or another for writing data to the memory cells and for reading data from the memory cells.
Usually in an MLC flash memory, each memory cell can have three or more threshold voltages (or can be in three or more states). As compared with a binary memory having only one threshold voltage, a more complicated control operation is required for writing and reading data in correspondence with each of the threshold voltages.
Hereinafter, a data write operation of a semiconductor memory device, which is an MLC flash memory, including a plurality of memory cells arranged in a matrix will be described.
First, a method for storing MLC data in a conventional MLC flash memory will be described in comparison with a method for storing MLC data in a conventional binary flash memory.
A MLC flash memory, which is a non-volatile semiconductor memory device, includes a plurality of memory cells which are usually formed of MOSFETs. Data is stored utilizing the phenomenon that the threshold voltage of each memory cell is changed in accordance with the amount of charge accumulated in a floating gate of the respective MOSFET.
FIG. 10 is a graph illustrating a distribution of threshold voltages of a plurality of memory cells provided in a general binary flash memory. The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. The reference threshold voltage at the center of the horizontal axis represents the voltage at which the data is read.
Usually, a representative binary NOR flash memory is in a data erased state when a floating gate of a memory cell does not have accumulated charges. This state is represented by data “1”. The binary NOR flash memory is in a data written state when a floating gate of a memory cell has negative charges (electrons) injected thereinto. This state is represented by data “0”.
The region of FIG. 10 which is lower than the reference threshold voltage shows a distribution of threshold voltages in the data erased state, and the region of FIG. 10 which is higher than the reference threshold voltage shows a distribution of threshold voltages in the data written state.
The threshold voltage of a memory cell is lower in the data erased state than in the data written state. Therefore, as long as the voltage applied to the control gate of a memory cell is at the same level, a higher magnitude of current flows in a memory cell in the data erased state than in a memory cell in the data written state. Namely, the magnitude of the current flowing in a memory cell is different in the data erased state from in the data written state. Whether there is data or not in the memory cell (“data storage state”) is checked, utilizing the difference in the magnitude of the current. This is referred to as a data read operation for verification. (A data verification operation described below is fundamentally the same as the data read operation for verification.)
A data read operation is performed by detecting the magnitude of the current flowing in a reference cell in which the above-mentioned reference threshold voltage is set and the magnitude of the current flowing in a memory cell from which data is to be read, and then comparing the magnitudes of the currents.
The magnitudes of the currents are specifically compared by detecting the magnitude of the current flowing in a bit line connected to the memory cell of interest and the magnitude of the current flowing in a bit line connected to the reference cell by a sense amplifier.
FIG. 11 is a graph illustrating a distribution of threshold voltages of a plurality of memory cells provided in a general quaternary flash memory. In this example, each of the memory cells in the quaternary flash memory stores 2-bit data. The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. Reference threshold voltages 1, 2 and 3 along the horizontal axis each represent the voltage at which the data is read.
Each memory cell in a quaternary flash memory can be in four states, i.e., a data erased state and three data written states. The threshold voltage of a memory cell is lowest in the data erased state. The threshold voltages of the three data written states are different. For performing a data read operation from a memory cell which can selectively be in four states, three reference voltages 1, 2 and 3 are set as shown in FIG. 11.
2-bit data which is written in the memory cells of the flash memory shown in FIG. 11 is defined as “11”, “10”, “01” or “00”. The memory cell storing data “11” has the lowest threshold voltage, and the memory cell storing data “00” has the highest threshold voltage. Data “11” corresponds to the data erased state. In the data written states corresponding to data “10”, “01” and “00”, the reference threshold voltages are set such that the variance in the distribution of threshold voltages is as small as possible among the plurality of memory cells.
A control operation for data write to an MLC flash memory such as the quaternary flash memory shown in FIG. 11 has the following problems.
A data write operation needs to be performed such that the distribution of threshold voltages corresponding to the data in a plurality of memory cells is within a relatively small range (i.e., such that the variance of the distribution is relatively small).
More specifically, the range of the distribution of threshold voltages corresponding to the data in the plurality of memory cells is enlarged when the data is read from the memory cells for reproduction than the range of the distribution of threshold voltages in the data write operation. Therefore, the margin for the lowest possible threshold voltage and the highest possible threshold voltage with respect to the reference voltage is reduced for data write.
In addition, the data needs to be read for reproduction efficiently from the memory cells for which three reference voltages are set.
FIG. 12 shows an exemplary algorithm for writing data to a quaternary flash memory. In the algorithm shown in FIG. 12, data write is performed in three steps, i.e., steps 1 through 3.
In each of steps 1 through 3, target data which should be stored in a memory cell and the current data stored in the memory cell are checked, so as to determine whether or not to execute data write to the memory cell. In the data write operation, the threshold voltage is set with more stringent conditions than the reference threshold voltage used for a data read operation, in order to guarantee a margin for over-time data deterioration after the data is written and also a margin for data read. The threshold voltage is also used for a data verification operation.
In steps 1 through 3, a prescribed write data pulse is applied to a control gate and a drain of each memory cell. Then, a data verification operation is performed (i.e., the reference threshold voltage is changed and a data read operation is performed), so as to check whether the threshold voltage of the memory cell has reached a desired level or not. When the threshold voltage has reached the desired level, application of the write data pulse is stopped. When the threshold voltage has not reached the desired level, application of the write data pulse is continued. The application of the write data pulse and the verification operation are repeated in this manner, so that the desired threshold voltage is set in the memory cell.
More specifically, data write is executed in accordance with whether or not the data needs to be written to the memory cells as shown in the table on the right of FIG. 12.
In step 1, the data write operation is performed to the memory cells in which the current data is “11” (data erased state) and the target data is “10”, “01” and “00”.
The data write operation is continued until the threshold voltage of all the memory cells to which data is to be written becomes reference threshold voltage 1′ which is the lowest possible value of the target data “10” or higher. (Reference threshold voltage 1′ is a value used for verification, which is set with more stringent conditions than reference threshold voltage 1 which is the lowest possible value of data “10” (FIG. 11) for data read. Similarly, reference threshold voltages 2′ and 2″ are set with more stringent conditions than reference threshold voltage 2, and reference threshold voltages 3′ and 3″ are set with more stringent conditions than reference threshold voltage 3.)
Reference threshold voltage 1′ is set to be higher than reference threshold voltage 1 used for reading data, in order to obtain, with certainty, a margin regarding the detection precision of a sense circuit used for reading the data and a margin for changes in the threshold voltage which is caused by over-time deterioration of data stored in the memory cell. For the same purpose, reference threshold voltage 2′ which is the highest possible value of target data “10” is set to be lower than reference threshold voltage 2 used for reading data.
For example, when a memory cell obtains a threshold voltage exceeding reference threshold voltage 2′ of target data “10” during the data write operation, the memory cell is in an over-program state, which is outside the threshold voltage range in which read of target data “10” is guaranteed. Therefore, when performing a data write operation in an MLC flash memory, it is important to prevent generation of memory cells in the over-program state by, for example, controlling the data write voltage.
In step 2, the data write operation is performed to the memory cells in which the target data is “01” or “00” and the current data is less than “01”. The details of the data write operation are substantially the same as in step 1.
In step 2, reference threshold voltage 2″ which is the lowest possible value of target data “01” is set to be higher than reference threshold voltage 2 (FIG. 11) which is the lowest possible value of data “01” for data read. Reference threshold voltage 3′ which is the highest possible value of target data “01” is set to be lower than reference threshold voltage 3 (FIG. 11) which is the highest possible value of data “01” for data read.
The data write operation is performed such that all the memory cells to which data is to be written obtain a threshold voltage in the range from reference threshold voltage 2″ (the lowest possible value of target data “01”) to reference threshold voltage 3′ (highest possible value of target data “01”).
In step 3, the data write operation is performed to the memory cells in which the target data is “00” and the current data is less than “00”. The details of the data write operation are substantially the same as in step 1.
In step 3, reference threshold voltage 3″ which is the lowest possible value of target data “00” is set to be higher than reference threshold voltage 3 (FIG. 11) which is the lowest possible value of data “00” for data read.
The data write operation is performed such that all the memory cells to which data is to be written obtain a threshold voltage greater than or equal to reference threshold voltage 3″ (the lowest possible value of target data “00”).
As described above, data can be written to a quaternary flash memory by the algorithm shown in FIG. 12.
Next, a phenomenon referred to as “array noise” will be described. “Array noise” causes as serious a problem as the over-program state to the data write operation.
Array noise is the following phenomenon. It is assumed, for example, that a prescribed memory cell and another memory cell are connected to a prescribed word line in a memory array. When data is written to the prescribed memory cell and the threshold voltage of the prescribed memory cell is changed, the threshold voltage of the another memory cell to which no data has been written is apparently changed.
FIG. 13 shows a part of a memory array of an MLC NOR flash memory. FIG. 13 shows four word lines WL1 through WL4, four bit lines BL1 through BL4, a source line SRC, and memory cells CELL11 through CELL44.
Sources of all the memory cells are commonly connected to the source line SRC. The word lines WL and the bit lines BL are perpendicular to each other.
The word lines WL1 through WL4 are commonly connected to a control gate of each of the memory cells connected thereto. The bit lines BL1 through BL4 are commonly connected to a drain of each of the memory cells connected thereto. Thus, the memory cells are arranged in a matrix.
Drains of two adjacent memory cells connected to each of bit lines BL1 through BL4 are connected to each other, and sources of two adjacent memory cells are connected to each other. For example, drains of the memory cells CELL11 and CELL21 are connected to each other, and the drains are connected to the bit line BL1. Sources of memory cells CELL21 and CELL31 are connected to each other, and the sources are connected to the source line SRC. Drains of memory cells CELL31 and CELL41 are connected to each other, and the drains are connected to the bit line BL1.
An operation of writing arbitrary data to the memory cells CELL21 through CELL23 connected to the word line WL2 from the state where data in all the memory cells are erased will be described. No data is written to the memory cell CELL24 connected to the word line WL2, and the memory cell CELL24 is kept in the data erased state.
Before the data write operation is performed, all the memory cells are in the data erased state. The threshold voltage is lowest in all the memory cells. As such, when a data read operation for verification is performed from the memory cells CELL21 through CELL24, a relatively high magnitude of current flows in the memory cells CELL21 through CELL24.
Thus, due to the parasitic resistance of the source line SRC, an increase in the output resistance of an output transistor in a driving circuit and the like, the voltage of the source line SRC floats relatively significantly from the original voltage (for example, the ground voltage).
As the data write operation to the memory cells CELL21 through CELL23 proceeds, the threshold voltage of the memory cells CELL21 through CELL23 rises. This reduces the magnitude of the current flowing in the memory cells CELL21 through CELL23, and thus the floating level of the voltage of the source line SRC from the ground voltage gradually decreases.
When the floating level of the voltage of the source line SRC decreases, the drain-source voltage of the memory cells CELL21 through CELL23 increases, and thus the magnitude of the current caused to flow by the data read operation for verification increases. Therefore, the sense amplifier incorrectly detects that the threshold voltage of the memory cells CELL21 through CELL23 has decreased.
The memory cell CELL24, which is not processed with data write and thus does not have the threshold voltage changed is connected to the source line SRC as well as the memory cells CELL21 through CELL23. Therefore, an increased magnitude of current flows in the memory cell CELL24 as a result of the data read operation for verification, and the sense amplifier incorrectly detects that the threshold voltage of the memory cell CELL24 has decreased.
This phenomenon is referred to as “array noise”. When array noise occurs, a memory cell, to which the data write operation and the verification operation have been completed, may be incorrectly determined as having a decreased threshold voltage as a result of the subsequent data read operation for verification and thus data is again written to the memory cell.
Such a malfunction by array noise causes a serious problem in an MLC flash memory, in which the threshold voltage of each memory cell needs to be precisely controlled in order to reduce the variance of the distribution of threshold voltages.
This does not result in a very serious problem in a binary flash memory for the following reason. In a binary flash memory also, the threshold voltage of a memory cell is increased when data is written again as compared with the threshold voltage in a usual data written state. However, in the binary flash memory, the margin for the lowest possible threshold voltage and the highest possible threshold voltage with respect to the reference voltage is larger than that in an MLC flash memory as shown in FIG. 10. Therefore, there is substantially no risk of the binary flash memory causing a malfunction when the data is read for reproduction.
By contrast, in an MLC flash memory, the margin for the lowest possible threshold voltage and the highest possible threshold voltage with respect to the reference voltage is smaller. Therefore, when the threshold voltages corresponding to data “10” and “01” (FIG. 11) become too high (“over-program”), data actually written may be different from the target data.
In addition, even when the data is written constantly with the same conditions, the floating level of the threshold voltage over the original voltage may gradually decrease.
In order to solve these problems, the amplitude (voltage value) and cycle (application time) of data pulses to be written to a memory cell need to be adjusted. However, even when such an adjustment is performed, a memory cell to which data can be written relatively easily may be incorrectly determined as not having been completely processed with data write after it is once determined as having been completely processed with data write in an early stage of a data write operation. In this case, data pulses having a high voltage are applied for a long period, which highly possibly causes an over-program state.
A similar phenomenon may occur also by, for example, a change in the sensing characteristics of the sense amplifier, which is caused by a change in the supply voltage.
Next, an operation of writing data to another MLC flash memory will be described with reference to FIG. 14.
A data write operation in an MLC f lash memory, which requires the threshold voltages of the memory cells to be precisely controlled, usually needs a longer time than in a binary flash memory.
In order to shorten the time required for the data write operation, an MLC flash memory usually includes a page buffer circuit for temporarily storing data to be written to memory cells. FIG. 14 shows a part of an MLC flash memory 400 including a page buffer circuit.
The MLC flash memory 400 includes a user interface circuit (hereinafter, referred to as a “UI circuit”) 410, a control bus 401, an address bus 402, and a data bus 403. The MLC flash memory 400 is externally operated via the control bus 401, the address bus 402, and the data bus 403, which are connected to the UI circuit 410.
The UI circuit 410 externally receives a signal via the control bus 401, the address bus 402, and the data bus 403, and analyzes the signal so as to control operations in the MLC flash memory 400. The UI circuit 410 is connected to a page buffer circuit 420 via a control bus 411, an address bus 412, and a data bus 413, and is also connected to a write state machine circuit (hereinafter, referred to as a “WSM circuit”) 430 via a control bus 414.
A page buffer circuit 420 temporarily stores data to be written to memory cells, and is controlled regarding data write by the UI circuit 410 via the control bus 411, the address bus 412, and the data bus 413.
The WSM circuit 430 controls operations of, for example, a memory array 460 upon receipt of an instruction to, for example, rewrite data in the memory cells. The WSM circuit 430 receives an instruction by a control signal from the UI circuit 410 via the control bus 414, and informs the state thereof to the UI circuit 410 by a signal 431. The WSM circuit 430 is connected to a read circuit (sense amplifier) 440, a write circuit (program circuit) 450, and the memory array 460 via the control buses 434, 435 and 436 respectively. The read circuit 440, the write circuit 450, and the memory array 460 are connected to each other via a read bus 461.
When instructed to write data by the UI circuit 410, the WSM circuit 430 outputs a control signal and address signals to the page buffer circuit 420 respectively via a control bus 432 and an address bus 433 so as to instruct the page buffer circuit 420 to output specific data which is to be written to memory cells. The page buffer circuit 420 outputs the instructed specific data to the WSM circuit 430 via a data bus 421.
The read circuit 440 receives a control signal from the WSM circuit 430 via the control bus 434 and thus reads data from the memory cells in the memory array 460. The memory cells from which the data is read are selected based on a control signal and address signals which are output by the WSM circuit 430 respectively via the control bus 436 and the address bus 433. The selected memory cells are activated by the WSM circuit 430.
Drains of the selected memory cells are connected to the read bus 461. The read circuit 440 confirms the threshold voltage (representing the data storage state) of each selected memory cell via the read bus 461, and then outputs the data read from the selected memory cells to the WSM circuit 430 via the data bus 441.
The WSM circuit 430 receives the specific data to be written (target data) from the page buffer circuit 420 via the data bus 421 and also receives data from the read circuit 440 via the data bus 441. Based on the current threshold voltage of each selected memory cell, the WSM circuit 430 determines whether or not to write data to each selected memory cell. A write data pulse as the determination result is output to the write circuit 450 via a data bus 437.
The WSM circuit 430 outputs a control signal to the memory array 460 via the control bus 436 so as to allow the memory array 460 to receive data. Then, the WSM circuit 430 outputs a control signal to the write circuit 450 via the control bus 435 so as to apply the write data pulse to the memory array 460. The write circuit 450 writes data corresponding to the write data pulse to the selected memory cells, by applying a high voltage signal to a bit line connected to a drain of each of the selected memory cells via the read bus 461 sequentially.
FIG. 15 shows a part of another MLC flash memory 500, which realizes a more efficient data write operation than the MLC flash memory 400 shown in FIG. 14.
The MLC flash memory 500 has a page mode read function of simultaneously reading data designated by a plurality of addresses and selecting necessary data from the read data.
Like the MLC flash memory 400 shown in FIG. 14, the MLC flash memory 500 includes a UI circuit 510, a control bus 501, an address bus 502, and a data bus 503. The MLC flash memory 500 is externally operated via the control bus 501, the address bus 502, and the data bus 503, which are connected to the UI circuit 510.
The UI circuit 510 externally receives a signal via the control bus 501, the address bus 502, and the data bus 503, and analyzes the signal so as to control operations in the MLC flash memory 500. The UI circuit 501 is connected to a page buffer circuit 520 via a control bus 511, an address bus 512, and a data bus 513, and is also connected to a WSM circuit 530 via a control bus 514.
The page buffer circuit 520 temporarily stores data to be written to memory cells, and is controlled regarding data write by the UI circuit 510 via the control bus 511, the address bus 512, and the data bus 513.
The WSM circuit 530 controls operations of, for example, a memory array 560 upon receipt of an instruction to, for example, rewrite data in the memory cells. The WSM circuit 530 receives an instruction by a control signal from the UI circuit 510 via the control bus 514, and informs the state thereof to the UI circuit 510 by a signal 531. The WSM circuit 530 is connected to an MLC logic circuit 580, a read circuit (sense amplifier) 540, a write circuit (program circuit) 550, and the memory array 560 via the control buses 533, 534, 535 and 536 respectively. The read circuit 540, the write circuit 550, and the memory array 560 are connected to each other via a read bus 561.
An address generation circuit (address controller) 570 receives a control signal and address signals from the WSM circuit 530 respectively via a control bus 538 and an address bus 539 so as to generate internal addresses. In the state where a leading address to which data is to be written is output to the address bus 539, the address generation circuit 570 sets, as the leading address, an address to be output to an address bus 571 based on an initialization signal received from the control bus 538. Then, the address generation circuit 570 increments the address based on a clock signal received from the control bus 538 and outputs the incremented address to the address bus 571.
The read circuit 540 receives a control signal from the WSM circuit 530 via the control bus 534 and thus reads data from the memory cells in the memory array 560. The memory cells from which the data is read are selected based on a control signal output by the WSM circuit 530 and address signals output by the address generation circuit 570 respectively via the control bus 536 and the address bus 571. The selected memory cells are activated by the WSM circuit 530.
Drains of the selected memory cells are connected to the read bus 561. The read circuit 540 confirms the threshold voltage (representing the data storage state) of each selected memory cell via the read bus 561, and then outputs the data read from the selected memory cells to a data multiplex circuit (hereinafter, referred to as a “MUX circuit”) 545 via the data bus 541.
The MUX circuit 545 receives an address signal from the address generation circuit 570 via the address bus 571. Based on the address signal, the MUX circuit 545 selects data to be output from the data received from the read circuit 540, and outputs the selected data to the MLC logic circuit 580 via a data bus 546.
The MLC logic circuit 580 receives a control signal which is output from the WSM circuit 530 via a control bus 533, target data which is output from the page buffer circuit 520 via a data bus 521, and the data which is selected by and output from the MUX circuit 545 via the data bus 546. Based on the current threshold voltage of each selected memory cell, the MLC logic circuit 580 determines whether or not to write data to each selected memory cell. A write data pulse is output as the determination result to the WSM circuit 530 via a data bus 581. Based on the write data pulse, the WSM circuit 530 outputs data, which indicates whether or not to write data to each selected memory cell, to the write circuit 550 via a data bus 537.
The WSM circuit 530 outputs a control signal to the memory array 560 via the control bus 536 so as to allow the memory array 560 to receive data. Then, the WSM circuit 530 outputs a control signal to the write circuit 550 via the control bus 535 so as to apply the write data pulse to the memory array 560. The write circuit 550 writes data corresponding to the write data pulse to the selected memory cells, by applying a high voltage signal to a bit line connected to a drain of each of the selected memory cells via the read bus 561 sequentially.
The page buffer circuit 520 of the MLC flash memory 500 shown in FIG. 15 has a feedback function as follows. Based on the control signal which is output from the WSM circuit 530 via a control bus 532, the page buffer circuit 520 can update the data designated by the address signal output from the address generation circuit 570 via the address bus 571 to feedback data generated by the MLC logic circuit 580. The feedback data is output to the page buffer circuit 520 from the MLC logic circuit 580 via a data bus 582.
FIG. 16 shows a truth table showing an exemplary operation of the MLC logic circuit 580 in a data write operation for a quaternary flash memory.
FIG. 16 shows a logic per memory cell which is used by the MLC logic circuit 580. The logic is equivalent to the logic used in the three-stage data write operation shown in FIG. 12. Steps 1, 2 and 3 of FIG. 16 respectively correspond to steps 1, 2 and 3 described above with reference to FIG. 12. In FIG. 16, “target” represents the target data, and “current” represents the current data. “Write” shows whether or not data is to be written in each of the memory cells. “L” indicates that no data is to be written, and “H” indicates that data is to be written.
FIG. 17 shows an exemplary logic circuit for realizing the logic shown in the truth table in FIG. 16. The logic circuit shown in FIG. 17 includes NAND circuits, NOR circuits, AND circuits and an OR circuit. Signals input to and output from the logic circuit shown in FIG. 17 are set as follows.
STP [1:0] is a signal representing the current step (FIG. 16). When the current step is step 1, STP[1:0] is 01. When the current step is step 2, STP[1:0] is 10. When the current step is step 3, STP[1:0] is 11. STP1 corresponds to the upper bit, and STP0 corresponds to the lower bit. For example, when the current step is step 1, STP[1:0] is 01, and therefore STP1 is 0 and STP0 is 1.
TGH and TGL respectively correspond to the upper bit and the lower bit of the target data (“target” in FIG. 16). For example, when the target data is 01, TGH is 0 and TGL is 1.
RDH and RDL respectively correspond to the upper bit and the lower bit of the current data (“current” in FIG. 16). For example, when the current data is 01, RDH is 0 and RDL is 1.
PROG represents the output data and corresponds to “write” in Table 16. When PROG is L, no data is written, and when PROG is H, data is written.
The MLC flash memory 400 shown in FIG. 14 and the MLC flash memory 500 shown in FIG. 15 are different from each other mainly in the following four points.
(1) An operation for determining whether or not to write data to a memory cell is performed by the WSM circuit 430 in the MLC flash memory 400, but by the MLC logic circuit 580 in the MLC flash memory 500.
(2) The address bus used for selecting memory cells to which data is to be written is controlled by the WSM circuit 430 in the MLC flash memory 400, but by the address generation circuit 570 in the MLC flash memory 500.
(3) The MLC flash memory 500 has a feedback function for rewriting the data in the page buffer circuit 520, whereas the MLC flash memory 400 does not have such a function.
(4) The MLC flash memory 500 has a page mode read function for selecting necessary data, whereas the MLC flash memory 400 does not have such a function.
Difference (1) will be described in detail. As described above with reference to FIGS. 16 and 17, the operation for determining whether or not to write data to a memory cell requires a complicated logic and a logic operation circuit for executing the logic. Even when the WSM circuit 430 of the MLC flash memory 400 includes a multi-purpose operation circuit, it takes a very long processing time to determine whether or not to write data by a combination of usual operations (for example, AND, OR, NOR and NAND). Under the circumstances, the MLC flash memory 500 performs the operation for determination by the MLC logic circuit 580, which is provided specifically for this purpose, and causes the WSM circuit 530 to process the result of the operation of the MLC logic circuit 580.
Difference (2) will be described in detail. In order to write data which is stored in a plurality of memory cells corresponding to a plurality of addresses, the internal addresses in the memory array need to be controlled by the control bus and the address bus. Such a control is performed by, for example, incrementing the leading address. The MLC flash memory 400 requires that the WSM circuit 430 should include an addition circuit and means for controlling the addition circuit in order to perform such a control of the address bus with the WSM circuit 430 (for example, in order to increment the address). The MLC flash memory 500 performs such a control of the addresses by the address generation circuit 570, which is provided specifically for this purpose.
Difference (3) will be described in detail. In the MLC flash memory 500, the page buffer circuit 520 has the above-mentioned feedback function. This prevents an over-program state which is otherwise caused by a change in the threshold voltage of memory cells by a data read operation for verification. Because of array noise described above, even a memory cell which is once determined as having reached the reference threshold voltage as a result of the data write operation may be determined as not having reached the reference threshold voltage by the subsequent data read operation for verification. In order to prevent data from being written again to the memory cell which is once determined as having reached the reference threshold voltage, the data stored in the page buffer circuit 520 is rewritten.
As is clear from FIG. 16, no data is written to the memory cells of which target data is “11” in the MLC flash memory 500.
Accordingly, for example, the data in the page buffer circuit 520 corresponding to a memory cell which is determined as having been completely processed with datawrite is rewritten as “11”. Owing to this rewriting, no write data pulse is additionally applied to the memory cell in the subsequent data write operation for verification, and thus generation of the over-program state by array noise can be alleviated.
As described above, the MLC flash memory 500 has a function of updating data stored in the page buffer circuit 520. The updated data (feedback data) is generated by the MLC logic circuit 580.
The updated data is generated by the MLC logic circuit 580 since the signal for generating the updated data is the same as the signal used for determining whether or not to write data. The updated data may be generated by a different circuit.
Difference (4) will be described in detail. Generally in an MLC flash memory, a data read operation is relatively slow. In order to prevent the overall operation from being lowered, a data output section for outputting data to an external circuit is provided with an additional function such as a page mode read function, a synchronous burst function or the like. With such specifications, the number of memory cells from which data is read at one time is larger than the number of memory cells from which data is read with usual specifications. Using the page mode read function, synchronous burst function or the like for controlling the data write operation, the speed of the data write operation is increased.
FIG. 18 shows a truth table showing an exemplary operation of the MLC logic circuit 580 in a data write operation for a quaternary flash memory, specifically for generating updated data using the feedback function. FIG. 19 shows an exemplary logic circuit for realizing the logic shown in FIG. 18.
In the logic structure shown in FIG. 18, data stored in the page buffer circuit 520 is rewritten to “11”, which represents the state where no data is written, when necessary.
The data stored in the page buffer circuit 520 may be rewritten to “11” in the state where a data write operation to the memory cell is completed; i.e., in step 1, the target data is “10” but data corresponding to “10” or more has been already written; in step 2, the target data is “01” but data corresponding to “01” or more has been already written; or in step 3, the target data is “00” but data corresponding to “00” has been already written.
In the memory cell in such a state, the target threshold voltage has already been reached, and no additional data write is necessary.
Therefore, there is no problem in rewriting the data stored in the page buffer circuit 520 to “11”. Such rewriting reduces the risk of the over-program state being generated.
The logic circuit shown in FIG. 19 includes a NAND circuit, NOR circuits, AND circuits and OR circuits. Signals input to and output from the logic circuit shown in FIG. 19 are set as described above with reference to FIGS. 16 and 17, except for feedback signals FBK1 and FBK0 which are output from the logic circuit.
FBK[1:0] after data rewrite (update) is “11” under the condition in which data rewrite to “11” is performed. In other conditions, FBK[1:0] is not changed. FBK1 corresponds to the upper bit, and FBK0 corresponds to the lower bit.
With reference to FIGS. 20 and 21, a data write operation performed by the WSM circuit 430 of the MLC flash memory 400 (FIG. 14) and the WSM circuit 530 of the MLC flash memory 500 (FIG. 15) will be described.
First, with reference to FIG. 20, a data write operation performed by the WSM circuit 430 of the MLC flash memory 400 (FIG. 14) will be described.
In the MLC flash memory 400, the elements used for data write are simple, and thus the role of the WSM circuit 430 in the control operation for data write is relatively important.
FIG. 20 is a flowchart illustrating an operation of writing data corresponding to one word. In FIG. 20, only the processing required for comparison with the operation performed by the MLC flash memory 500 and an MLC flash memory according to the present invention is shown. In actuality, the WSM circuit 430 performs other processing as well. A part of the operation does not need to be as illustrated in FIG. 20.
In step S4000, the WSM circuit 430 processes addresses of memory cells to which data is to be written. According to the simplest procedure, the address of the first memory cell among the memory cells to which data is to be written is set as the leading address in the first cycle of operation, and then the address is incremented.
In step S4001, the WSM circuit 430 outputs the resultant address to the memory array 460 as an internal address. Then, the memory array 460 is put into a state in which data can be read (step S4002). The memory cell in the memory array 460 designated by the internal address is activated and data is read therefrom (step S4003).
When a special control is necessary for reading data stored in the page buffer circuit 420, such a control is performed at this point. In the example of FIG. 20, the page buffer circuit 420 is assumed to output data corresponding to internal addresses, for the sake of simplicity. The same is applied to FIG. 21 (below).
In step S4004, based on the result of the data read from the page buffer circuit 420 and the result of the data read from the memory cell, the WSM circuit 430 determines whether or not to write data to the memory cell by performing an operation based on, for example, the truth table shown in FIG. 16.
The operation, although relatively complicated, needs to be performed by the WSM circuit 430 in the MLC flash memory 400 since the MLC flash memory 400 does not include a circuit specifically provided for this purpose (such as the address generation circuit 570 in the MLC flash memory 500).
In step S4005, the WSM circuit 430 outputs data to be written generated based on the determination result in step S4004 to the write circuit 450. The memory array 460 is put into a state where data can be written (step S4006), and the write control 450 is controlled to write data to the memory cell (step S4007).
Thus, data is written to the memory cells in the memory array 460. All the data is written by repeating such processing by the number of data required to be written.
With reference to FIG. 21, a data write operation performed by the WSM circuit 530 of the MLC flash memory 500 (FIG. 15) will be described. FIG. 21 is a flowchart illustrating an operation of writing data corresponding to one page.
Instep S5000, the WSM circuit 530 sets an internal address as the leading address of the page address.
In step S5001, the WSM circuit 530 puts the memory array 560 into a state where the data can be read. In step S5002, data is read from a memory cell in the memory array 560. Owing to page mode read, data corresponding to all the addresses in a page can be read simultaneously. Therefore, after this step, data corresponding to the addresses designated by the address generation circuit 570 among all the addresses are sequentially output from the MUX circuit 545.
In step S5003, the WSM circuit 530 puts the memory array 560 into a state where data can be written. Then, data to be written generated by the MLC logic circuit 580 is read (step S5004) and output to the write circuit 550 (step S5005). Thus, data is written to the memory cell in the memory array 560 (step S5006). In step S5007, it is determined whether or not all the data corresponding to one page to be written has been written. When all the data has been written, the data write operation is completed. When all the data has not been written, the address is updated (step S5008). When it is not necessary to repeat the data read operation for the same page, the processing is returned to step S5004 after the address is updated and the data write operation is repeated.
Thus, data corresponding to one page is written to the memory cells in the memory array 560. All the data is written by repeating such processing by the number of data required to be written.
Comparing the flowcharts in FIGS. 20 and 21, the MLC flash memory 500 does not need to determine whether or not to write data by the WSM circuit 530. Therefore, the operation is quite simple.
The number of times that the state where data can be read and the state where data can be written of the memory array 560 are switched is smaller than in the case of the memory array 460. Therefore, relatively time-consuming processing such as, for example, switching of the voltage applied to the memory array 560 in the MLC flash memory 500 can be reduced. Thus, the speed of the data write operation can be increased.
Processing regarding addresses is mainly simply incrementing the addresses, and therefore can be done by a circuit specifically provided for this purpose (such as the address generation circuit 570).
As described above, the MLC flash memory 500 shown in FIG. 15 allows the speed of the data write operation to be increased and the structure of the WSM circuit 530 to be simplified, as compared to the MLC flash memory 400 shown in FIG. 14.
As can be appreciated from the above, the conventional MLC flash memories allow the speed of the data write operation to be increased and the structure of the WSM circuit to be simplified to some extent.
However, the data write operation in the conventional MLC flash memories requires generation of internal addresses and input/output control of necessary data. Therefore, the WSM circuit is still large and complicated, and thus the speed of the data write operation cannot be significantly increased. The risk of array noise being generated is not completely eliminated.